EN0-001 Leak Questions

ARM Accredited Engineer Questions and Answers

Question 25

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

Options:

5 cycles

7 cycles

8 cycles

15 cycles

Question 26

Which of the following is an advantage of the single-step debug technique?

Options:

It allows a complete trace of real-time program execution to be captured

It reduces the number of pins required to connect the debugger to the processor

It allows examination of the system state before and after execution of a statement

It requires only one change to the program source code

Question 27

Which of the following operations would count as intrusive to normal processor operation?

Options:

Tracing using Embedded Trace Macrocell (ETM)

Halt mode debugging

Monitor mode debugging

Using the Performance Monitor Unit

Question 28

The effect of clicking the Stop button in a debugger is to:

Options:

Put the processor(s) into debug state.

Force the processor to execute a BKPT instruction

Hold the processor in a Reset condition

Re-initialize the memory contents.

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ARM Accredited Engineer Questions and Answers

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CompTIA

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