EN0-001 Exam Dumps : ARM Accredited Engineer

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

An undefined instruction will cause an Undefined Instruction exception to be taken when:

In a loop termination test, how might a programmer indicate to the compiler that the loop iteration count limit is divisible by four?