EN0-001 Exam Dumps : ARM Accredited Engineer

Under which of the following data-sharing scenarios would cache maintenance operations be necessary?

Cortex-A series processors contain event counting hardware which can be used to profile and benchmark code. The counters for these are programmed using:

An interrupt handler contains the following instruction sequence at the end. The purpose of these instructions is to clear the interrupt request in the interrupt controller and then safely re-enable interrupts.

STR r0, [r1] ; write to interrupt controller register to clear interrupt request

CPSIE i ; re-enable IRQ interrupts

Which of the following instructions should be placed at position in order to ensure that the interrupt controller sees the write before interrupts are re-enabled?