EN0-001 Exam Dumps : ARM Accredited Engineer

Which of the following processor resources do NOT have to be saved or modified by the Linux scheduler during context switch?

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

In which type of storage will the compiler preferentially place frequently accessed variables?